Jop Opening

Cosmik System LLC



Verify complex design blocks using equally complex SV/UVM verification environments

Develop and execute pre-silicon verification test plans

Develop directed and random verification tests to validate block and IP functionality

Develop verification components and tools

Develop verification functional coverage using industry standard coverage analysis tools/methods

Debug regression fails

Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

Required Skills and Experience:

8 or more years of proven verification experience on large ASIC development projects in a hardware development setting

Strong background in SystemVerilog and UVM verification methodologies

Solid experience in IP or SOC level verification on ASIC based products

IP experience in high speed IO protocols like DDR, USB, PCIE, Ethernet is desirable

PHY verification experience, including some amount of mixed signal verification experience is desirable

Strong debug skills and experience with debug tools such as DVE/Verdi

Proficiency in Object Oriented programming, computer architecture and data structures

Strong analytical/problem solving skills and pronounced attention to details

Strong interpersonal and communication skills

Must be comfortable working across geographies


Minimum Bachelor's Degree required in (Engineer’s degree in telecommunications and computer science from)


Over 9 years’ experience in ASIC verification, with several successful and functional devices

Over 5 years’ experience in the embedded software design, including drivers, frame work and lab validation

Proficiency in HW and protocol modeling in C++ and SystemVerilog

Proficiency in Object Oriented design

Proficiency in verification methodology: UVM

Pre and post silicon test planning, and execution

Experience in FPGA design (RTL) and verification (Altera and Xilinx)

Proficiency in tools and languages: C, C++, SystemC, Verilog, SystemVerilog, Tcl/Expect,...

Experience with many Telecom and Datacom protocols: SONET/SDH, PDH, OTN, SPI3, GFP, VCAT/LCAS,...

Strong analytical and problem solving skills

Strong academic background: B. sc. Math and B. sc. Computer Science

Experience mentoring junior engineers

Have worked closely with various teams: marketing, ASIC designers, SW designers, Board designers


Hardware: Verilog, System Verilog: interfaces, constrained random verification techniques, assertions, functional coverage, SystemC, UVM/OVM and VMM methodologies Knowledge, RTL coding, FPGA design and verification, PLI and DPI, Synopsys and Cadence tools

C, C++, Smalltalk, Lisp, scheme, Pascal, Ada, Tcl, Expect, Perl, Python

Data Modeling and Object-Oriented Programming (OOP)

Real Time Programming

Algorithmic and data structures (trees, graphs, lists,...)

Relational databases (SQL, Microsoft Access, Dbase)

Operating systems: Unix, Linux, Windows, RTOS (VxWorks)

DS1/E1, DS3/E3, SONET/SDH, OTN (ODU0/ODU1/ODU2/ODUFLEX). GFP and PPP encapsulation, Ethernet Over SONET (EoS), ATM (Networking, Traffic management, Inverse Multiplexing), Ethernet 10/100/GigE

Virtual Concatenation (VC) and Link Capacity Adjustment Scheme (LCAS), High/Low order

Bus Interfaces: SDRAM, M8260, SPI3, Ethernet, Gige, Telecom Bus Interface


  • Req Ref No: CMiK0023
  • Job Title: Verification Engineer
  • Location: Austin, TX (REMOTE)
  • Duration: 6.0 months